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19-1641; Rev 1; 1/01
Low-Cost, Low-Power, 8-Bit DACs with 2-Wire Serial Interface in SOT23
General Description
The MAX5380/MAX5381/MAX5382 are low-cost, 8-bit digital-to-analog converters (DACs) in miniature 5-pin SOT23 packages, with a simple 2-wire serial interface that allows communication with multiple devices. The MAX5380 has an internal +2V reference and operates from a +2.7V to +3.6V supply. The MAX5381 has an internal +4V reference and operates from a +4.5V to +5.5V supply. The MAX5382 operates over the full +2.7V to +5.5V supply range and has an internal reference equal to 0.9 x VDD. The fast-mode I2CTM-compatible serial interface allows communication at data rates up to 400kbps, minimizing board space and reducing interconnect complexity in many applications. Each device is available with one of four factory-preset addresses (see Selector Guide). These DACs also include an output buffer, a low-power shutdown mode, and a power-on reset that ensures the DAC outputs are at zero when power is initially applied. In shutdown mode, supply current is reduced to less than 1A and the output is pulled down to GND with a 10k resistor.
Features
o 8-Bit Accuracy in a Miniature 5-Pin SOT23 o Wide +2.7V to +5.5V Supply Range (MAX5382) o Low 230A max Supply Current o 1A Shutdown Mode o Buffered Output Drives Resistive Loads o Low-Glitch Power-On Reset to Zero DAC Output o Fast I2C-Compatible Serial Interface o <5% Full-Scale Error (MAX5382) o <1LSB max INL/DNL
MAX5380/MAX5381/MAX5382
Ordering Information
PART MAX5380_EUK-T MAX5381_EUK-T MAX5382_EUK-T TEMP. RANGE -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 5 SOT23 5 SOT23 5 SOT23
Applications
Automatic Tuning (VCO) Power-Amplifier Bias Control Programmable Threshold Levels Automatic Gain Control Automatic Offset Adjustment
PART MAX5380LEUK MAX5380MEUK MAX5380NEUK MAX5380PEUK MAX5381LEUK MAX5381MEUK MAX5381NEUK MAX5381PEUK MAX5382LEUK MAX5382MEUK MAX5382NEUK MAX5382PEUK ADDRESS 0x60 0x62 0x64 0x66 0x60 0x62 0x64 0x66 0x60 0x62 0x64 0x66
Selector Guide
REFERENCE (V) +2.0 +2.0 +2.0 +2.0 +4.0 +4.0 +4.0 +4.0 0.9 x VDD 0.9 x VDD 0.9 x VDD 0.9 x VDD TOP MARK ADMN ADMZ ADFN ADMP ADMV ADNB ADNH ADML ADMX ADND ADNJ ADNT
Typical Operating Circuit
+2.7V TO +5.5V
VDD C VDD PX.0/SDA PX.1/SCL GND SDA SCL
Pin Configuration
TOP VIEW
MAX5382
GND
OUT
OUT
1
5
SCL
GND 2 VDD 3
MAX5380 MAX5381 MAX5382
4 SDA
I2C is a trademark of Philips Corp.
SOT23-5
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Low-Cost, Low-Power, 8-Bit DACs with 2-Wire Serial Interface in SOT23 MAX5380/MAX5381/MAX5382
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V OUT, SCL, SDA to GND ...........................................-0.3V to +6V Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70C) 5-Pin SOT23 (derate 7.1mW/C above +70C).............571mW Operating Temperature Ranges MAX538_ _EUK-T .............................................-40C to +85C Storage Temperature Range .............................-65C to +150C Maximum Junction Temperature .....................................+150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +2.7V to +3.6V (MAX5380), VDD = +4.5V to +5.5V (MAX5381), VDD = +2.7V to +5.5V (MAX5382); RL = 10k; CL = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are TA = +25C.) PARAMETER STATIC ACCURACY Resolution Integral Linearity Error Differential Linearity Error Offset Error Offset Error Supply Rejection Offset Error Temperature Coefficient Full-Scale Error Full-Scale Error Supply Rejection Full-Scale Error Temperature Coefficient DAC OUTPUT MAX5380 Internal Reference (Note 5) REF MAX5381 MAX5382 Output Load Regulation Output Resistance DYNAMIC PERFORMANCE Voltage Output Slew Rate Output Settling Time Digital Feedthrough Digital-Analog Glitch Impulse Wake-Up Time Positive and negative To 1/2 LSB, 50k and 50pF load (Note 6) Code = 0, all digital inputs from 0 to VDD Code 127 to 128 From software shutdown 0.4 20 2 40 50 V/s s nVs nVs s Code = 255, 0 to 100A Code = 0, 0 to 100A VOUT = 0 to VDD, power-down mode 1.8 3.6 0.85 x VDD 2 4 0.9 x VDD 0.5 0.5 10 2.2 4.4 0.95 x VDD LSB k V INL DNL (Note 1) Guaranteed monotonic (Note 2) MAX5382 (Notes 2, 3) (Note 2) Code = 255 MAX5380/MAX5381 MAX5382 MAX5380/MAX5381 MAX5382 MAX5380/MAX5381 MAX5382 40 10 60 3 1 10 5 50 1 8 1 1 25 Bits LSB LSB mV dB ppm/C % of ideal FS dB ppm/C SYMBOL CONDITIONS MIN TYP MAX UNITS
Code = 255, MAX5380/MAX5281 (Note 4) Code = 255
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Low-Cost, Low-Power, 8-Bit DACs with 2-Wire Serial Interface in SOT23
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +3.6V (MAX5380), VDD = +4.5V to +5.5V (MAX5381), VDD = +2.7V to +5.5V (MAX5382); RL = 10k; CL = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are TA = +25C.) PARAMETER POWER REQUIREMENTS MAX5380 Supply Voltage VDD MAX5381 MAX5382 Supply Current DIGITAL INPUTS (SCL, SDA) Input Low Voltage Input High Voltage Input Hysteresis Input Capacitance Input Leakage Current Pulse Width of Spike Suppressed DIGITAL OUTPUT (SDA, open drain) Output Low Voltage VOL ISINK = 3mA ISINK = 6mA VIH(MIN) to VIL(MAX), bus capacitance = 10pF to 400pF ISINK = 3mA ISINK = 6mA 0.4 0.6 250 ns 250 V VIL VIH VHYS CIN IIN tSP 0 (Note 7) 0.7 x VDD 0.05 x VDD 10 10 50 0.3 x VDD V V V pF A ns IDD No load, all digital inputs at 0 or VDD, code = 255 Shutdown mode 2.7 4.5 2.7 150 3.6 5.5 5.5 230 1 A V SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5380/MAX5381/MAX5382
Output Fall Time
tOF
TIMING CHARACTERISTICS
(Figure 3; VDD = +2.7V to +3.6V (MAX5380), VDD = +4.5V to +5.5V (MAX5381), VDD = +2.7V to +5.5V (MAX5382); RL = 10k; CL = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are TA = +25C.) (Note 7) PARAMETER SCL Clock Frequency Bus Free Time Between a STOP and a START Condition Hold Time Repeated for a START Condition Low Period of the SCL Clock High Period of the SCL Clock Setup Time for a Repeated START Condition Data Hold Time Data Setup Time SYMBOL fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT CONDITIONS MIN 0 1.3 0.6 1.3 0.6 0.6 0 100 0.9 TYP MAX 400 UNITS kHz s s s s s s ns
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Low-Cost, Low-Power, 8-Bit DACs with 2-Wire Serial Interface in SOT23 MAX5380/MAX5381/MAX5382
TIMING CHARACTERISTICS (continued)
(Figure 3; VDD = +2.7V to +3.6V (MAX5380), VDD = +4.5V to +5.5V (MAX5381), VDD = +2.7V to +5.5V (MAX5382); RL = 10k; CL = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are TA = +25C.) (Note 7) PARAMETER Rise Time of Both SDA and SCL Signals Fall Time of Both SDA and SCL Signals Setup Time for STOP Condition Capacitive Load for Each Bus Line Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: SYMBOL tr tf tSU:STO Cb 0.6 400 CONDITIONS MIN TYP MAX 300 300 UNITS ns ns s pF
Guaranteed from code 5 to code 255. The offset value extrapolated from the range over which the INL is guaranteed. MAX5382 tested at VDD = +5V 10%. MAX5380 tested at VDD = +3V 10%, MAX5381 tested at VDD = 5V 10%. Actual output voltages at full scale are 255/256 x VREF. Output settling time is measured by taking the code from code 5 to 255, and from code 255 to 5. Guaranteed by design.
Typical Operating Characteristics
(VDD = +3.0V (MAX5380), VDD = +5.0V (MAX5381/MAX5382); RL = 10k, TA = +25C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. CODE
MAX5380/1/2-01
INTEGRAL NONLINEARITY vs. SUPPLY VOLTAGE
MAX5380/1/2-02
INTEGRAL NONLINEARITY vs. TEMPERATURE
MAX5380/1/2-03
0.075 0.050 0.025
0
0
-0.05 INL (LSB) INL (LSB)
-0.05
INL (LSB)
0 -0.025 -0.050 -0.075 -0.100
-0.10
-0.10
-0.15
-0.15
-0.20 0 50 100 150 CODE 200 250 300 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
-0.20 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
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Low-Cost, Low-Power, 8-Bit DACs with 2-Wire Serial Interface in SOT23
Typical Operating Characteristics (continued)
(VDD = +3.0V (MAX5380), VDD = +5.0V (MAX5381/MAX5382); RL = 10k, TA = +25C, unless otherwise noted.)
MAX5380/MAX5381/MAX5382
DIFFERENTIAL NONLINEARITY vs. CODE
MAX5380/1/2-04
DIFFERENTIAL NONLINEARITY vs. SUPPLY VOLTAGE
MAX5380/1/2-05
DIFFERENTIAL NONLINEARITY vs. TEMPERATURE
MAX5380/1/2-06
0 -0.02
0 -0.02
0.04 0.02 DNL (LSB) 0 -0.02 -0.04 -0.06 -0.08 0 50 100 150 CODE 200 250
DNL (LSB)
-0.06
DNL (LSB) 2.5 3.0 3.5 4.0 4.5 5.0 5.5
-0.04
-0.04
-0.06
-0.08
-0.08
-0.10 300 SUPPLY VOLTAGE (V)
-0.10 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
TOTAL UNADJUSTED ERROR vs. CODE
MAX5380/1/2-07
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX5380/1/2-08
OFFSET ERROR vs. TEMPERATURE
MAX5380/1/2-09
0.45 0.30 0.15 TUE (LSB) 0 -0.15 -0.30 -0.45 -0.60 0 50 100 150 CODE 200 250
0
0
-0.5 VOS (mV)
-0.5 OFFSET ERROR (mV) 2.5 3.0 3.5 4.0 4.5 5.0 5.5
-1.0
-1.0
-1.5
-1.5
-2.0 300 SUPPLY VOLTAGE (V)
-2.0 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
FULL-SCALE ERROR vs. SUPPLY VOLTAGE
3 2 FULL-SCALE ERROR (LSB) 1 0 -1 -2 NO LOAD -3 2.5 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) -1.2 5.5 -3
MAX5380/1/2-10
FULL-SCALE ERROR vs. TEMPERATURE
3 2 FULL-SCALE ERROR (LSB) FULL-SCALE ERROR (%) 1 0 MAX5382 -1 -2 -0.4 -0.8 -1.2 100 MAX5380 MAX5381
MAX5380/1/2-11
SUPPLY CURRENT vs. SUPPLY VOLTAGE
180
MAX5380/1/2-12
MAX5381 MAX5380 MAX5382
1.2 0.8 0.4 0 -0.4 -0.8
1.2 0.8 FULL-SCALE ERROR (%) SUPPLY CURRENT (A) 0.4 0
200 MAX5381 MAX5380 MAX5382
160 140 120 100 80 60 40 20 0 2.5
-40
-20
0
20
40
60
80
3.0
3.5
4.0
4.5
5.0
5.5
TEMPERATURE (C)
SUPPLY VOLTAGE (V)
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Low-Cost, Low-Power, 8-Bit DACs with 2-Wire Serial Interface in SOT23 MAX5380/MAX5381/MAX5382
Typical Operating Characteristics (continued)
(VDD = +3.0V (MAX5380), VDD = +5.0V (MAX5381/MAX5382); RL = 10k, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
NO LOAD
MAX5380/1/2-13
SUPPLY CURRENT vs. CODE
MAX5380/1/2-14
160 155 SUPPLY CURRENT (A)
160 155 MAX5381, VDD = +5.0V SUPPLY CURRENT (A) 150 MAX5382, VDD = +5.0V 145 140 135 NO LOAD 130 MAX5380, VDD = +5.0V MAX5380, VDD = +3.0V
MAX5381 150 145 140 135 130 -40 -20 0 20 40 60 80 100 TEMPERATURE (C) MAX5382 MAX5380
0
32
64
96
128 160 192 224 CODE
256
SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5380/1/2-15
SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE
MAX5380/1/2-16
1.0 0.8 SUPPLY CURRENT (A)
1.0 0.8 SUPPLY CURRENT (A)
0.6
0.6 VDD = +5.0V 0.4 VDD = +3.0V 0.2
0.4
0.2
0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
0 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
OUTPUT LOAD REGULATION
4.5 VOUT FULL SCALE (V) 4.0 3.5 3.0 2.5 2.0 1.5 C D E 0.1 0 0 1 2 3 4 5 6 7 8 9 10 LOAD CURRENT (mA) A: MAX5361/MAX5362, VDD = 4.5V FULL-SCALE OR SOURCING B: MAX5360, FULL-SCALE, VDD = 2.7V SINKING, VDD = 5.0V SOURCING C: MAX5360, FULL-SCALE, VDD = 2.7V SOURCING D: ZERO CODE, VDD = 2.7V SINKING E: ZERO CODE, VDD = 5.5V SINKING B VOUT ZERO CODE (V) 0.2 VDD 2V/div OUT 50mV/div A
MAX5380/1/2-17
OUTPUT VOLTAGE ON POWER-UP
MAX5380/1/2-18
4s/div
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Low-Cost, Low-Power, 8-Bit DACs with 2-Wire Serial Interface in SOT23
Typical Operating Characteristics (continued)
(VDD = +3.0V (MAX5380), VDD = +5.0V (MAX5381/MAX5382); RL = 10k, TA = +25C, unless otherwise noted.)
MAX5380/MAX5381/MAX5382
OUTPUT VOLTAGE EXITING SHUTDOWN
MAX5380/1/2-19
OUTPUT VOLTAGE ENTERING SHUTDOWN
MAX5380/1/2-20
OUTPUT SETTLING FROM 1/4 FS TO 3/4 FS
MAX5380/1/2-21
OUT 500mV/div
OUT 500mV/div
OUT 0.5V/div
SDA 3V/div
SDA 3V/div
SDA 3V/div
10s/div MAX5380, SHDN TO 0x80
1s/div MAX5380, 0x80 TO SHDN MAX5380
1s/div
OUTPUT SETTLING FROM 3/4 FS TO 1/4 FS
MAX5380/1/2-22
OUTPUT SETTLING 1LSB STEP UP
MAX5380/1/2-23
OUTPUT SETTLING 1LSB STEP DOWN
MAX5380/1/2-24
OUT 0.5V/div
OUT 20mV/div AC-COUPLED
OUT 20mV/div AC-COUPLED
SDA 3V/div
SDA 3V/div
SDA 3V/div
1s/div MAX5380
2s/div MAX5380, 0x7F TO 0x80
2s/div MAX5380, 0x80 TO 0x7F
Pin Description
PIN 1 2 3 4 5 NAME OUT GND VDD SDA SCL DAC Voltage Output Ground Power-Supply Input Serial Data Input Serial Clock Input FUNCTION
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Low-Cost, Low-Power, 8-Bit DACs with 2-Wire Serial Interface in SOT23 MAX5380/MAX5381/MAX5382
VDD
VREF
REF CURRENTSTEERING DAC 255 SDA SCL CONTROL LOGIC DATA LATCH 8 SERIAL INPUT REGISTER MAX5380 MAX5381 MAX5382 OUT
SW1
SW2
SW255
10k
OUT
GND
Figure 1. Functional Diagram
Figure 2. Current-Steering Topology
Table 1. Unipolar Code Output Voltage
OUTPUT VOLTAGE DAC CODE MAX5380 1111 1111 1000 0000 0000 0001 0000 0000 2V x (255 / 256) +1V 7.8mV 0 MAX5381 4V x (255 / 256) +2V 15.6mV 0 MAX5382 0.9 x VDD x (255 / 256) 0.9 x VDD / 2 0.9 x VDD / 256 0
Detailed Description
The MAX5380/MAX5381/MAX5382 voltage-output, 8-bit digital-to-analog converters (DACs) offer full 8-bit performance with less than 1LSB integral nonlinearity error and less than 1LSB differential nonlinearity error, ensuring monotonic performance. The devices use a simple 2-wire, fast-mode I2C-compatible serial interface that operates at up to 400kHz. The MAX5380/MAX5381/ MAX5382 include an internal reference, an output buffer, and a low-current shutdown mode, which make these devices ideal for low-power, highly integrated applications (See Figure 1. Functional Diagram).
currents is steered to the DAC output. The current is then converted to a voltage across a resistor, and this voltage is buffered by the output buffer amplifier. Output Voltage Table 1 shows the relationship between the DAC code and the analog output voltage. The 8-bit DAC code is binary unipolar with 1LSB = VREF / 256. The MAX5380/ MAX5381 have a full-scale output voltage of (+2V 1LSB) and (+4V - 1LSB), respectively, set by the internal references. The MAX5382 has a full-scale output voltage of (0.9 x VDD - 1LSB). Output Buffer The DAC voltage output is an internally buffered unitygain follower that typically slews at 0.4V/s. The output can swing from 0 to full scale. With a 1/4 FS to 3/4 FS output transition, the amplifier outputs typically settle to 1/2LSB in less than 5s when loaded with 10k in parallel with 50pF. The buffer amplifiers are stable with any combination of resistive loads >10k and capacitive loads <50pF.
Analog Section
The MAX5380/MAX5381/MAX5382 employ a currentsteering DAC topology as shown in Figure 2. At the core of the DAC is a reference voltage-to-current converter (V/I) that generates a reference current. This current is mirrored to 255 equally weighted current sources. DAC switches control the outputs of these current mirrors so that only the desired fraction of the total current-mirror
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Low-Cost, Low-Power, 8-Bit DACs with 2-Wire Serial Interface in SOT23 MAX5380/MAX5381/MAX5382
SDA tSU: DAT tLOW SCL tHD: STA tR START CONDITION tHIGH tF REPEATED START CONDITION STOP CONDITION START CONDITION tHD: DAT tSU: STA tHD: STA tSU: STO tBUF
Figure 3. 2-Wire Serial Interface Timing Diagram
VDD C SDA SCL SCL RS* VDD
after a loss of power. The output glitch at startup is typically less than 50mV. Shutdown Mode The MAX5380/MAX5381/MAX5382 include a softwarecontrolled shutdown mode that reduces the supply current to <1A. All internal circuitry is disabled, and an internal 10k resistor is placed from OUT to GND to ensure 0V at OUT while in shutdown. The device enters shutdown in less than 5s and exits shutdown in less than 50s.
MAX5380M 2V REFERENCE SDA OUT
OFFSET ADJUSTMENT
SCL
VDD
Digital Section
Serial Interface The MAX5380/MAX5381/MAX5382 use a simple 2-wire serial interface requiring only two I/O lines (2-wire bus) of a standard microprocessor (P) port. Figure 3 shows the timing diagram for signals on the 2-wire bus. The two bus lines (SDA and SCL) must be high when the bus is not in use. The MAX5380/MAX5381/ MAX5382 are receive-only devices (slaves) and must be controlled by a bus master device. Figure 4 shows a typical application where up to four devices can be connected to the bus, provided they have different address settings. External pull-up resistors are not necessary on these lines (when driven by push-pull drivers), though these DACs can be used in applications where pull-up resistors are required (such as in I2C systems) to maintain compatibility with existing circuitry. The serial interface operates at SCL rates up to 400kHz. The SDA state is allowed to change only while SCL is low, with the exception of START and STOP conditions as shown in Figure 5. Each transmission consists of a START condition sent by the bus master
9
MAX5381N 4V REFERENCE SDA OUT
THRESHOLD ADJUSTMENT
SCL
VDD
MAX5382P VDD REFERENCE SDA OUT *RS IS OPTIONAL.
GAIN ADJUSTMENT
Figure 4. Typical Application Circuit
Power-On Reset The MAX5380/MAX5381/MAX5382 have a power-on reset circuit to set the DAC's output to 0 when VDD is first applied or when VDD dips below 1.7V (typ). This ensures that unwanted DAC output voltages will not occur immediately following a system startup, such as
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Low-Cost, Low-Power, 8-Bit DACs with 2-Wire Serial Interface in SOT23 MAX5380/MAX5381/MAX5382
SDA
SCL START CONDITION STOP CONDITION
define a write or read protocol, sets the device's power mode (SHDN). The device is powered-down when SHDN is set to one. During a device search routine, the MAX5380/MAX5381/MAX5382 acknowledge both options (SHDN = 0 or SHDN = 1), but do not change their power state if a stop condition (or restart) is issued immediately. The second byte (DAC data) must be sent/received for the device to update both power mode and DAC output. DAC Data The 8-bit DAC data is decoded as straight binary MSB first with 1LSB = VREF / 256 and converted into the corresponding analog voltage as shown in Table 1. After receiving the data byte, the devices acknowledge its receipt and expect a STOP condition, at which point the DAC output is updated. The MAX5380/MAX5381/MAX5382 update the output and the power mode only if the second byte is clocked in (SHDN = 0) or out (SHDN = 1) of the device. When SHDN = 1, the master will read all ones when clocking out a data byte. The MAX5380/MAX5381/MAX5382 do not drive SDA except for the acknowledge bit. I2C Compatibility The MAX5380/MAX5381/MAX5382 are compatible with existing I2C systems. SCL and SDA are high-impedance inputs; SDA has an open drain that pulls the data line low during the 9th clock pulse. Figure 7 shows a typical I2C application. The communication protocol supports standard I2C 8-bit communications. The general call address is ignored, and CBUS formats are not supported. The devices' address is compatible with the 7-bit I2C addressing protocol only. No 10-bit formats
Figure 5. START and STOP Conditions
device, followed by the MAX5380/MAX5381/MAX5382s' preset slave address, a power-mode bit, the DAC data, and finally, a STOP condition (Figure 6). The bus is then free for another transmission. SDA's state is sampled and therefore must remain stable while SCL is high. Data is transmitted in 8-bit bytes. Nine clock cycles are required to transfer each byte to the MAX5380/MAX5381/MAX5382. Release SDA during the 9th clock cycle since the selected device acknowledges receipt of the byte by pulling SDA low during this time. A series resistor on the SDA line may be needed if the master's output is forced high while the selected device acknowledges (Figure 4). Slave Address The MAX5380/MAX5381/MAX5382 are available with one of four preset slave addresses. Each address option is identified by the suffix L, M, N, or P added to the part number. The address is defined as the 7MSBs sent by the master after a START condition. The address options are 0x60, 0x62, 0x64, 0x66 (left justified with LSB set to 0). The 8th bit, typically used to
SLAVE ADDRESS BYTE SDA 0 MSB 1 START CONDITION * L M N P A1 A2 00 0 1 1 1 0 1 *SEE ORDERING INFORMATION. 1 1 0 0 A1 A2 LSB 8 9 SHDN ACK D7 MSB 10 D6 D5
DAC CODE D4 D3 D2 D1 D0 LSB 17 18 STOP CONDITION ACK
Figure 6. A Complete Serial Transmission
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Low-Cost, Low-Power, 8-Bit DACs with 2-Wire Serial Interface in SOT23
VDD C SDA SCL
Applications Information
Digital Inputs and Interface Logic
The serial 2-wire interface has logic levels defined as VIL = 0.3 x VDD and VIH = 0.7 x VDD. All inputs include Schmitt trigger buffers to accept slow-transition interfaces. This means that optocouplers can interface directly to the MAX5380/MAX5381/MAX5382 without additional external logic. The digital inputs are compatible with CMOS logic levels and must not be driven with voltages higher than VDD.
MAX5380/MAX5381/MAX5382
SCL
VDD
MAX5380L 2V REFERENCE SDA OUT
OFFSET ADJUSTMENT
Power-Supply Bypassing and Layout
SCL VDD
MAX5381M 4V REFERENCE OUT SDA
THRESHOLD ADJUSTMENT
SCL
VDD
MAX5382N VDD REFERENCE OUT SDA
Careful printed circuit board layout is important for best system performance. To reduce crosstalk and noise injection, keep analog and digital signals separate. Ensure that the ground return from GND to the supply ground is short and low impedance; a ground plane is recommended. Bypass VDD with a 0.1F capacitor to ground as close as possible to the device. If the supply is excessively noisy, connect a 10 resistor in series with the supply and VDD and add additional capacitance.
GAIN ADJUSTMENT
Chip Information
TRANSISTOR COUNT: 2910
Figure 7. Typical I2C Application
are supported. RESTART protocol is supported, but an immediate STOP condition is necessary to update the DAC. The 8th bit of the address byte, typically used to indicate a read or write protocol, is used in the MAX5380/ MAX5381/MAX5382 to enter or exit shutdown mode. When MAX5380/MAX5381/MAX5382 are addressed in I2C read mode, they enter shutdown mode.
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Low-Cost, Low-Power, 8-Bit DACs with 2-Wire Serial Interface in SOT23 MAX5380/MAX5381/MAX5382
Package Information
SOT5L.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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